1. Field of the Invention
This invention relates to the formation of floating gate field effect transistors and to the formation of nonvolatile memories using floating gate transistors.
2. Description of the Related Art
Nonvolatile memories are used in a variety of electronic devices for storing configuration data, program data and other data to be accessed on a repeated basis in the electronic devices. Recent applications have placed particular emphasis on programmable nonvolatile memories such as EEPROMs and especially on the flash memory configuration of EEPROMs. Flash memories have the comparative advantage of greater flexibility for changing the data in the EEPROMs either during the manufacturing process or after the electronic devices have been placed in the field. One typical implementation of a flash memory is illustrated in U.S. Pat. No. 5,416,349 to Bergemont, which describes a flash memory having a common source, buried bit line architecture as well as a configuration of a floating gate field effect transistor. The common source, buried bit line architecture of the Bergemont patent has the advantage of relatively high density, which is an important consideration for achieving low cost. Cost is a very important consideration for flash memories because the number of applications for which flash memories are suitable is highly cost sensitive. The Bergemont patent's architecture provides a high density of memory cells, which can provide a low cost flash memory. On the other hand, high density itself is insufficient to ensure that a flash memory is suitable for many applications. Low voltage operation, the ability to undergo repeated programming, and predictable operation are also important to determining how suitable a particular flash memory is for different applications.
Memory storage in flash EEPROMs is accomplished by selectively storing charge on the floating gate of a floating gate transistor. A generalized representation of a floating gate transistor similar to that used in the Bergemont patent's flash EEPROM is illustrated in FIG. 1. Field isolation regions 12 are formed at the surface of a substrate 10, nominally doped P-type, with the field isolation regions 12 defining the active device regions and providing lateral isolation between adjacent devices formed in and on the surface of the substrate 10. A gate oxide layer 14 for the floating gate transistor covers the active device regions of the substrate 10. A gate electrode structure is formed on the gate oxide layer 14 and consists of a floating gate 16 of doped polysilicon covered by an interlayer dielectric layer 18 which is in turn covered by a control gate 20 of doped polysilicon. Oxide spacer structures 22 are provided on either side of the gate electrode structure. The inner edges of source/drain regions 24 define a channel region at the surface of the substrate, with a source/drain region extending from either side of the gate electrode structure to the adjacent field isolation regions 12. Frequently, the source/drain regions 24 have a lightly doped drain (LDD) structure in which an inner, more lightly doped portion of the source/drain region is aligned with the edge of the gate electrode structure, and a more heavily doped portion of the source/drain region 24 is aligned with the outer edge of the oxide spacer structure 22. In some instances, including the floating gate transistors described in the Bergemont patent, an asymmetric source/drain structure is adopted, in which the source electrode is provided with an LDD structure and the drain electrode has more a uniform doping. Such an asymmetric floating gate structure provides advantages for the programming of the floating gate transistor, since the electric field will be greater adjacent the drain electrode in this configuration.
Programming charge is stored onto the floating gate 16 of the FIG. 1 structure in an electron or hole tunneling process. It is typically necessary to apply comparatively high voltages between the control gate and one of the source/drain regions 24 to effect the tunneling through the gate oxide layer 14 during programming of the FIG. 1 floating gate transistor. It is known in the art that the required programming voltage can be reduced by providing a thinner oxide layer beneath the floating gate electrode through which programming occurs. Such a thinner tunneling oxide region is typically provided as a relatively small window beneath the gate electrode and adjacent the drain electrode. The tunneling oxide layer is formed thinner than the rest of the thicker gate oxide layer because excessive Icakage might occur if the entire gate oxide layer were made thin which would reduce the stability of the memory. It is, however, difficult to form a tunneling window of a fixed size and with a high quality of oxide. Methods for forming tunneling oxide windows are complicated and inclusion of appropriate tunneling oxide windows for floating gate transistors significantly increase the cost of the flash memory.
Another disadvantage of the floating gate transistor illustrated in FIG. 1 and of the method of making that transistor is that the source/drain electrodes require a significant implantation to ensure that their resistance is sufficiently low to provide good device performance. The required high level of ion implantation causes a variety of problems. For example, the heavy ion implantation dosage renders the substrate amorphous where the source/drain regions are to be formed. Recrystallization of the substrate in the source/drain regions is then performed in an annealing process which can produce defects in the recrystallized material, or which can lead to excessive levels of diffusion from the source/drain regions. Excessive diffusion from the source/drain regions can make the channel region beneath the gate electrode structure narrower than is desired, compromising device performance.